代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/18028/771226
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:21:56 09/19/2007
// Design Name:
/
www.eeworm.com/read/18028/771227
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:50:06 09/21/2007
// Design Name:
/
www.eeworm.com/read/18028/771228
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:46:12 09/22/2007
// Design Name:
/
www.eeworm.com/read/18028/771229
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:47:48 09/19/2007
// Design Name:
/
www.eeworm.com/read/18028/771230
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:44:16 09/22/2007
// Design Name:
/
www.eeworm.com/read/18028/771231
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c7
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771232
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c7
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771233
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c7
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771234
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:32:48 09/19/2007
// Design Name:
/
www.eeworm.com/read/18028/771235
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:36:39 09/18/2007
// Design Name:
/