代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
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www.eeworm.com/read/18028/771206
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:38:47 10/04/2007
// Design Name:
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www.eeworm.com/read/18028/771207
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:45:19 07/27/2007
// Design Name:
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www.eeworm.com/read/18028/771208
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:15:32 08/12/2007
// Design Name:
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www.eeworm.com/read/18028/771209
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c9
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771210
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:32:30 08/19/2007
// Design Name:
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www.eeworm.com/read/18028/771211
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:50:09 10/09/2007
// Design Name:
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www.eeworm.com/read/18028/771212
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03:01:45 10/06/2007
// Design Name:
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www.eeworm.com/read/18028/771213
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:19:18 08/12/2007
// Design Name:
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www.eeworm.com/read/18028/771214
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:41:40 08/12/2007
// Design Name:
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www.eeworm.com/read/18028/771215
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:01:28 07/27/2007
// Design Name:
/