代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5586013
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_keeper is
port(
o : inout vl_logic
);
end x_keeper;
www.eeworm.com/read/159314/5586015
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_buf is
port(
o : out vl_logic;
i : in vl_logic
);
end x_buf;
www.eeworm.com/read/159314/5586027
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s1_s9 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : intege
www.eeworm.com/read/159314/5586032
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s1_s2 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : intege
www.eeworm.com/read/159314/5586035
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s1_s18 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integ
www.eeworm.com/read/159314/5586045
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s18 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer
www.eeworm.com/read/159314/5586048
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s4_s9 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : intege
www.eeworm.com/read/159314/5586057
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s36 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer
www.eeworm.com/read/159314/5586064
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_opad is
port(
pad : out vl_logic
);
end x_opad;
www.eeworm.com/read/159314/5586065
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s2_s2 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : intege