代码搜索：verilog hdl 开发教程
找到约 10,000 项符合「verilog hdl 开发教程」的源代码
代码结果 10,000
www.eeworm.com/read/18028/771251
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:16:14 09/23/2007
// Design Name:
/
www.eeworm.com/read/18028/771252
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\work\ISE\c10
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/18028/771253
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:39:19 08/06/2007
// Design Name:
/
www.eeworm.com/read/18028/771254
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\work\ISE\c10
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/18028/771255
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:54:01 08/07/2007
// Design Name:
/
www.eeworm.com/read/18028/771256
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:50:43 08/09/2007
// Design Name:
/
www.eeworm.com/read/18028/771257
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\work\ISE\c10
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/18028/771258
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:51:03 08/09/2007
// Design Name:
/
www.eeworm.com/read/18028/771259
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:12:17 08/07/2007
// Design Name:
/
www.eeworm.com/read/18028/771260
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:55:39 08/09/2007
// Design Name:
/