代码搜索：verilog hdl 开发教程
找到约 10,000 项符合「verilog hdl 开发教程」的源代码
代码结果 10,000
www.eeworm.com/read/18028/771241
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:59:33 10/08/2007
// Design Name:
/
www.eeworm.com/read/18028/771242
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:00:27 10/08/2007
// Design Name:
/
www.eeworm.com/read/18028/771243
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:57:44 10/08/2007
// Design Name:
/
www.eeworm.com/read/18028/771244
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:05:17 09/24/2007
// Design Name:
/
www.eeworm.com/read/18028/771245
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c10
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/18028/771246
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:31:38 09/23/2007
// Design Name:
/
www.eeworm.com/read/18028/771247
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:52:31 09/24/2007
// Design Name:
/
www.eeworm.com/read/18028/771248
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:49:50 09/24/2007
// Design Name:
/
www.eeworm.com/read/18028/771249
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:44:13 09/23/2007
// Design Name:
/
www.eeworm.com/read/18028/771250
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c10
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym