代码搜索：verilog hdl 开发教程
找到约 10,000 项符合「verilog hdl 开发教程」的源代码
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www.eeworm.com/read/18028/771161
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c5
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771162
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:55:52 09/12/2007
// Design Name:
/
www.eeworm.com/read/18028/771163
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:01:57 10/08/2007
// Design Name:
/
www.eeworm.com/read/18028/771164
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:41:16 09/12/2007
// Design Name:
/
www.eeworm.com/read/18028/771165
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:48:19 10/08/2007
// Design Name:
/
www.eeworm.com/read/18028/771166
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\work\ISE\c11
SET speedgrade = -12
SET simulationfiles = Structural
SET asysym
www.eeworm.com/read/18028/771167
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:20:51 08/29/2007
// Design Name:
/
www.eeworm.com/read/18028/771168
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:22:09 09/02/2007
// Design Name:
/
www.eeworm.com/read/18028/771169
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:32:11 08/29/2007
// Design Name:
/
www.eeworm.com/read/18028/771170
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:40:02 09/02/2007
// Design Name:
/