代码搜索：verilog hdl 开发教程
找到约 10,000 项符合「verilog hdl 开发教程」的源代码
代码结果 10,000
www.eeworm.com/read/18028/771151
verilog
memory_initialization_radix=10;
memory_initialization_vector = 10000 , 10000
, 9999
, 9998
, 9997
, 9995
, 9993
, 9991
, 9988
, 9985
, 9981
, 9977
, 9973
, 9968
www.eeworm.com/read/18028/771152
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c5
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771153
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:41:02 10/08/2007
// Design Name:
/
www.eeworm.com/read/18028/771154
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:50:44 09/09/2007
// Design Name:
// Modul
www.eeworm.com/read/18028/771155
verilog
##############################################################
#
# Xilinx Core Generator version i+IP+122117
# Date: Sun Sep 09 14:00:29 2007
#
########################################################
www.eeworm.com/read/18028/771156
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:39:47 09/21/2007
// Design Name:
/
www.eeworm.com/read/18028/771157
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c5
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771158
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:25:38 09/12/2007
// Design Name:
/
www.eeworm.com/read/18028/771159
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:43:26 09/09/2007
// Design Name:
// Modul
www.eeworm.com/read/18028/771160
verilog
##############################################################
#
# Xilinx Core Generator version i+IP+122117
# Date: Sun Sep 09 15:50:11 2007
#
########################################################