代码搜索：verilog hdl 开发教程
找到约 10,000 项符合「verilog hdl 开发教程」的源代码
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www.eeworm.com/read/18028/771131
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:36:33 09/17/2007
// Design Name:
/
www.eeworm.com/read/18028/771132
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:38:08 09/12/2007
// Design Name:
/
www.eeworm.com/read/18028/771133
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c6
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771134
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:56:38 09/16/2007
// Design Name:
/
www.eeworm.com/read/18028/771135
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:56:22 09/16/2007
// Design Name:
/
www.eeworm.com/read/18028/771136
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:37:08 10/09/2007
// Design Name:
/
www.eeworm.com/read/18028/771137
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:32:26 09/17/2007
// Design Name:
/
www.eeworm.com/read/18028/771138
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:09:08 09/14/2007
// Design Name:
// Modul
www.eeworm.com/read/18028/771139
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:08:02 09/14/2007
// Design Name:
// Modul
www.eeworm.com/read/18028/771140
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:53:06 09/12/2007
// Design Name:
/