代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
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www.eeworm.com/read/172733/9694862
vhd my_testbench1.vhd
--===========================================================================----
--
-- T E S T B E N C H tesetbench1 - CPU09 Testbench.
--
-- www.OpenCores.Org - September 2003
-- This cor
www.eeworm.com/read/172733/9694898
vhd miniuart3_testbench.vhd
--===========================================================================--
--
-- MiniUart3 Test Bench
--
--
-- John Kent 16th January 2004
--
--
------------------------------------------
www.eeworm.com/read/172338/9713174
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/412239/11208789
v testbench_wd_reg.v
// testbench for write data register
`include "wd_reg.v"
module top;
reg sysclk;
reg [31:0] WD_Bus_Write;
reg WD_DBE, WD_Load;
wire [31:0] WD_DOUT;
integer file; //the number
www.eeworm.com/read/412239/11208826
v testbench_regfile2.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 3-29-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/412239/11208837
v testbench_regfile4.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 4-3-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/412239/11208843
v testbench_arm7.v
/////////////////////////////////////////////////////////////////
// ARM7 TOP LEVEL TEST BENCH v1.0, 4-6-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/412239/11208871
v testbench_addr_reg.v
`include "addr_reg.v"
module top;
reg [31:0] AR_Bus_Alu, AR_Bus_PC, AR_Bus_PC_4;
reg [1:0] AR_Bus_Sel;
reg sysclk;
wire [31:0] AR_Output_Bus;
integer file; //the number for the
www.eeworm.com/read/412239/11208873
v testbench_regfile3.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 3-29-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/200611/15428687
vhd 53_counter_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d