代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/31975/1030427
v testbench_regfile3.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 3-29-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/32675/1035494
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/40270/1138763
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/487718/1234982
vhd 41_generic_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
www.eeworm.com/read/487718/1235050
vhd 53_counter_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d
www.eeworm.com/read/464255/1532020
vhd testbench_ac97_if.vhd
-------------------------------------------------------------------------------
-- TESTBENCH_standalone.vhd
-------------------------------------------------------------------------------
-- Filena
www.eeworm.com/read/464255/1532059
vhd testbench_ac97_if.vhd
-------------------------------------------------------------------------------
-- TESTBENCH_standalone.vhd
-------------------------------------------------------------------------------
-- Filena
www.eeworm.com/read/456726/1602629
vhd 41_generic_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
www.eeworm.com/read/456726/1602697
vhd 53_counter_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d