代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/18515/792131
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/18518/792764
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/18532/793273
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/18590/796271
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/18628/798015
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/31975/1030373
v testbench_wd_reg.v
// testbench for write data register
`include "wd_reg.v"
module top;
reg sysclk;
reg [31:0] WD_Bus_Write;
reg WD_DBE, WD_Load;
wire [31:0] WD_DOUT;
integer file; //the number
www.eeworm.com/read/31975/1030397
v testbench_regfile2.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 3-29-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/31975/1030408
v testbench_regfile4.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 4-3-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/31975/1030414
v testbench_arm7.v
/////////////////////////////////////////////////////////////////
// ARM7 TOP LEVEL TEST BENCH v1.0, 4-6-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/31975/1030426
v testbench_addr_reg.v
`include "addr_reg.v"
module top;
reg [31:0] AR_Bus_Alu, AR_Bus_PC, AR_Bus_PC_4;
reg [1:0] AR_Bus_Sel;
reg sysclk;
wire [31:0] AR_Output_Bus;
integer file; //the number for the