代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/316450/13522557
vhd 41_generic_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
www.eeworm.com/read/302512/13833596
txt crc_3_testbench.txt
`timescale 1ns/1ns
module crc_3_test;
parameter size=4,
with=3;
reg clk,rest;
reg start;
reg[size-1:0]Din;
wire[size+with-1:0]Vout;
always #2 clk=~clk;
initial
begin
www.eeworm.com/read/487618/6506441
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/347629/11653003
vhd 41_generic_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
www.eeworm.com/read/347629/11653314
vhd 53_counter_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d
www.eeworm.com/read/258747/11845912
txt rs_testbench.v.txt
/////////////////////////////////////////////////////////////////////
//// ////
//// High Speed Reed Solomon Encoder
www.eeworm.com/read/153614/12021073
vhd 41_generic_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
www.eeworm.com/read/153614/12021342
vhd 53_counter_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d
www.eeworm.com/read/151305/12220517
vhd 41_generic_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
www.eeworm.com/read/151305/12220730
vhd 53_counter_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d