代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
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www.eeworm.com/read/431956/8645231
txt spi2-testbench.txt
SPI_Master_tb.v - Verilog source for SPI module Test Bench
Copyright (C) 2007 Steven Yu
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Gener
www.eeworm.com/read/387422/8684787
v can_testbench_defines.v
/* Mode register */
`define CAN_MODE_RESET 1'h1 /* Reset mode */
/* Bit Timing 0 register value */
`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*
www.eeworm.com/read/384728/8848998
vhd 41_generic_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
www.eeworm.com/read/384728/8849382
vhd 53_counter_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d
www.eeworm.com/read/284185/8955708
vhd 41_generic_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
www.eeworm.com/read/284185/8956074
vhd 53_counter_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d
www.eeworm.com/read/379944/9171771
v testbench_wd_reg.v
// testbench for write data register
`include "wd_reg.v"
module top;
reg sysclk;
reg [31:0] WD_Bus_Write;
reg WD_DBE, WD_Load;
wire [31:0] WD_DOUT;
integer file; //the number
www.eeworm.com/read/379944/9171821
v testbench_regfile2.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 3-29-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/379944/9171841
v testbench_regfile4.v
/////////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 4-3-2000 //
// ECE 371 EMR, Spring 2000 //
//
www.eeworm.com/read/379944/9171851
v testbench_arm7.v
/////////////////////////////////////////////////////////////////
// ARM7 TOP LEVEL TEST BENCH v1.0, 4-6-2000 //
// ECE 371 EMR, Spring 2000 //
//