代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/31975/1030377
v testbench_controller.v
// File to test the arm controller
// Created Amit Pandey 04/04/2000
// Controller tested on this by
// Jon Moeller, Daryl K., Matt Crum
// 04/05/2000
// Updated the instantiation and added test
www.eeworm.com/read/31975/1030379
v testbench_simplememory.v
// Testbed for SDRAM model (simple)
// written by Chris Fester 4-2-00
`include "SimpleMemory.v"
`include "Memoryside.v"
module top;
reg [31:0] outsideAddr;
wire [31:0] A;
wire [31:0] D;
wire nRA
www.eeworm.com/read/31975/1030386
v testbench_cpuside.v
// Simple tester for CPUside
`include "CPUside.v"
`define DEBUG
module top;
// All regs
reg [31:0] A;
tri [31:0] D;
reg nMREQ, nRW, sysclk, reset;
wire nWAIT;
reg [1:0] MAS
www.eeworm.com/read/31975/1030387
v testbench_avlmemory.v
// Testbed for SDRAM model with AVL implementation
// written by Chris Fester 4-5-00
`include "AVLMemory.v"
`include "Memoryside.v"
module top;
reg [31:0] outsideAddr;
wire [31:0] A;
wire [
www.eeworm.com/read/31975/1030388
v testbench_regfile.v
// testbench for register file
// really really incomplete in number of tests!
`include "regfile.v"
module top;
reg sysclk;
reg [`ADDRLEN-1:0] RF_Addr_A,RF_Addr_B,RF_Addr_C,RF_Addr_Write;
www.eeworm.com/read/31975/1030399
v testbench_barrel.v
`include "barrel.v"
module top_Barrel_Shifter;
reg [31:0] Input_Bus;
reg [1:0] Shift_Type;
reg [4:0] Shift_Amt;
reg Cin,Enable;
wire [31:0] Output_Bus;
wire Cout;
integer i;
www.eeworm.com/read/31975/1030401
v testbench_alu.v
/////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 3-28-2000 //
// ECE 371 EMR, Spring 2000 //
// By Steve B
www.eeworm.com/read/31975/1030424
v testbench_memory.v
// Simple tester for Memory Interface
// NB. Run in a maximised xterm, with a small font on a very hi-res screen.
`include "MemoryInterface.v"
`define DEBUG
module top;
// All regs
reg [31:0
www.eeworm.com/read/31975/1030428
v testbench_dedsec.v
///// testbench_dedsec.v
`include "clock.v"
module top;
integer x,y;
reg [127:0] data;
reg [25:0] dedsec;
reg pass;
c1 clock(sysclk);
always
begin
@(posedge sys
www.eeworm.com/read/32675/1035408
ndo can_testbench.ndo
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model for Module can_top
vcom -87 -explicit can_t