代码搜索:testbench

找到约 2,392 项符合「testbench」的源代码

代码结果 2,392
www.eeworm.com/read/18590/796233

udo can_testbench.udo

## Project Navigator simulation template: can_testbench.udo ## You may edit this file to control your simulation.
www.eeworm.com/read/18590/796268

v can_testbench.v

// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" `include "can_testbench_defines.v" module can_testbench(); parameter Tp = 1; paramet
www.eeworm.com/read/18590/796289

fdo can_testbench.fdo

## NOTE: Do not edit this file. ## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jan 11 10:15:14 中国标准时间 2005 ## vlib work vlog can_register_asyn_syn.v vlog can_register_asyn.v vlog can_regi
www.eeworm.com/read/18628/797929

ndo can_testbench.ndo

## NOTE: Do not edit this file. ## Auto generated by Project Navigator for VHDL Post-Translate Simulation ## vlib work ## Compile Post-Translate Model for Module can_top vcom -87 -explicit can_t
www.eeworm.com/read/18628/797977

udo can_testbench.udo

## Project Navigator simulation template: can_testbench.udo ## You may edit this file to control your simulation.
www.eeworm.com/read/18628/798012

v can_testbench.v

// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" `include "can_testbench_defines.v" module can_testbench(); parameter Tp = 1; paramet
www.eeworm.com/read/18628/798033

fdo can_testbench.fdo

## NOTE: Do not edit this file. ## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jan 11 10:15:14 中国标准时间 2005 ## vlib work vlog can_register_asyn_syn.v vlog can_register_asyn.v vlog can_regi
www.eeworm.com/read/31975/1030375

v testbench_booth.v

///////////////////////////////////////////////////////////// // Verilog Test Bench v2.0, 3-29-2000 // // ECE 371 EMR, Spring 2000 // // By Steve B