代码搜索：testbench

找到约 2,392 项符合「testbench」的源代码

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fdo can_testbench.fdo

## NOTE: Do not edit this file. ## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jan 11 10:15:14 中国标准时间 2005 ## vlib work vlog can_register_asyn_syn.v vlog can_register_asyn.v vlog can_regi
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www.eeworm.com/read/18518/792678

ndo can_testbench.ndo

## NOTE: Do not edit this file. ## Auto generated by Project Navigator for VHDL Post-Translate Simulation ## vlib work ## Compile Post-Translate Model for Module can_top vcom -87 -explicit can_t
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www.eeworm.com/read/18518/792726

udo can_testbench.udo

## Project Navigator simulation template: can_testbench.udo ## You may edit this file to control your simulation.
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www.eeworm.com/read/18518/792761

v can_testbench.v

// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" `include "can_testbench_defines.v" module can_testbench(); parameter Tp = 1; paramet
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www.eeworm.com/read/18518/792782

fdo can_testbench.fdo

## NOTE: Do not edit this file. ## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jan 11 10:15:14 中国标准时间 2005 ## vlib work vlog can_register_asyn_syn.v vlog can_register_asyn.v vlog can_regi
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www.eeworm.com/read/18532/793187

ndo can_testbench.ndo

## NOTE: Do not edit this file. ## Auto generated by Project Navigator for VHDL Post-Translate Simulation ## vlib work ## Compile Post-Translate Model for Module can_top vcom -87 -explicit can_t
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www.eeworm.com/read/18532/793235

udo can_testbench.udo

## Project Navigator simulation template: can_testbench.udo ## You may edit this file to control your simulation.
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www.eeworm.com/read/18532/793270

v can_testbench.v

// synopsys translate_off `include "timescale.v" // synopsys translate_on `include "can_defines.v" `include "can_testbench_defines.v" module can_testbench(); parameter Tp = 1; paramet
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www.eeworm.com/read/18532/793291

fdo can_testbench.fdo

## NOTE: Do not edit this file. ## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jan 11 10:15:14 中国标准时间 2005 ## vlib work vlog can_register_asyn_syn.v vlog can_register_asyn.v vlog can_regi
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www.eeworm.com/read/18590/796185

ndo can_testbench.ndo

## NOTE: Do not edit this file. ## Auto generated by Project Navigator for VHDL Post-Translate Simulation ## vlib work ## Compile Post-Translate Model for Module can_top vcom -87 -explicit can_t
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