代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/225948/14510018
v testbench_avlmemory.v
// Testbed for SDRAM model with AVL implementation
// written by Chris Fester 4-5-00
`include "AVLMemory.v"
`include "Memoryside.v"
module top;
reg [31:0] outsideAddr;
wire [31:0] A;
wire [
www.eeworm.com/read/225948/14510020
v testbench_regfile.v
// testbench for register file
// really really incomplete in number of tests!
`include "regfile.v"
module top;
reg sysclk;
reg [`ADDRLEN-1:0] RF_Addr_A,RF_Addr_B,RF_Addr_C,RF_Addr_Write;
www.eeworm.com/read/225948/14510041
v testbench_barrel.v
`include "barrel.v"
module top_Barrel_Shifter;
reg [31:0] Input_Bus;
reg [1:0] Shift_Type;
reg [4:0] Shift_Amt;
reg Cin,Enable;
wire [31:0] Output_Bus;
wire Cout;
integer i;
www.eeworm.com/read/225948/14510045
v testbench_alu.v
/////////////////////////////////////////////////////////////
// Verilog Test Bench v2.0, 3-28-2000 //
// ECE 371 EMR, Spring 2000 //
// By Steve B
www.eeworm.com/read/225948/14510090
v testbench_memory.v
// Simple tester for Memory Interface
// NB. Run in a maximised xterm, with a small font on a very hi-res screen.
`include "MemoryInterface.v"
`define DEBUG
module top;
// All regs
reg [31:0
www.eeworm.com/read/225948/14510099
v testbench_dedsec.v
///// testbench_dedsec.v
`include "clock.v"
module top;
integer x,y;
reg [127:0] data;
reg [25:0] dedsec;
reg pass;
c1 clock(sysclk);
always
begin
@(posedge sys
www.eeworm.com/read/217286/14970511
h testbench_arch.h
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ /
// \ \ \/
// \ \ Copyright (c) 2003-2004 Xi
www.eeworm.com/read/217286/14970512
obj testbench_arch.obj
www.eeworm.com/read/217283/14970698
h testbench_arch.h
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ /
// \ \ \/
// \ \ Copyright (c) 2003-2004 Xi
www.eeworm.com/read/217283/14970699