代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/464255/1532028
do ac97_fifo.do
vsim work.testbench_ac97_fifo
add wave test_no
add wave Bus2IP_Reset Bus2IP_Clk
### AC97 signals
# I/O pins
add wave bit_clk sync sdata_out sdata_in ac97reset_n
# control signals
add w
www.eeworm.com/read/464255/1532065
do ac97_fifo.do
vsim work.testbench_ac97_fifo
add wave test_no
add wave Bus2IP_Reset Bus2IP_Clk
### AC97 signals
# I/O pins
add wave bit_clk sync sdata_out sdata_in ac97reset_n
# control signals
add w
www.eeworm.com/read/168399/5447262
do ac97_fifo.do
vsim work.testbench_ac97_fifo
add wave test_no
add wave Bus2IP_Reset Bus2IP_Clk
### AC97 signals
# I/O pins
add wave bit_clk sync sdata_out sdata_in ac97reset_n
# control signals
add w
www.eeworm.com/read/379944/9171862
do_verilog
#!/bin/csh
cp ../bitg/$1.imem arm7.imem
cp ../bitg/$1.dmem arm7.dmem
cp ../bitg/$1.dmemr arm7.dmemr
cp ../bitg/$1.regsr arm7.regsr
verilog testbench_arm7.v
echo register comparison
diff arm7.regout ar
www.eeworm.com/read/353698/10431128
do_verilog
#!/bin/csh
cp ../bitg/$1.imem arm7.imem
cp ../bitg/$1.dmem arm7.dmem
cp ../bitg/$1.dmemr arm7.dmemr
cp ../bitg/$1.regsr arm7.regsr
verilog testbench_arm7.v
echo register comparison
diff arm7.regout ar
www.eeworm.com/read/225948/14510084
do_verilog
#!/bin/csh
cp ../bitg/$1.imem arm7.imem
cp ../bitg/$1.dmem arm7.dmem
cp ../bitg/$1.dmemr arm7.dmemr
cp ../bitg/$1.regsr arm7.regsr
verilog testbench_arm7.v
echo register comparison
diff arm7.regout ar
www.eeworm.com/read/217279/14971340
ref hdllib.ref
EN ccdout NULL D:/MY_DESIGN/ISE/LXJ/CCDOUT/CCDOUT.vhd sub00/vhpl00 1178166288
AR ccdout_tbw testbench_arch D:/MY_DESIGN/ISE/LXJ/CCDOUT/CCDOUT_tbw.vhw sub00/vhpl03 1179393252
EN ccdout_tbw NULL D:/MY
www.eeworm.com/read/17769/758323
vhd bin27seg_vhd_vec_tst.vhd
--另外，行为级的描述常常被用来产生仿真时的测试向量（testbench）文件。
--例如对于本节开始处提到的LED译码电路，可以编写如下测试向量文件。
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bin27seg_vhd_vec_tst IS
END bi
www.eeworm.com/read/17970/768293
vhd bin27seg_vhd_vec_tst.vhd
--另外，行为级的描述常常被用来产生仿真时的测试向量（testbench）文件。
--例如对于本节开始处提到的LED译码电路，可以编写如下测试向量文件。
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bin27seg_vhd_vec_tst IS
END bi
www.eeworm.com/read/31975/1030421
do_verilog
#!/bin/csh
cp ../bitg/$1.imem arm7.imem
cp ../bitg/$1.dmem arm7.dmem
cp ../bitg/$1.dmemr arm7.dmemr
cp ../bitg/$1.regsr arm7.regsr
verilog testbench_arm7.v
echo register comparison
diff arm7.regout ar