代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/16360/670510
vhw b.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 11:36:11 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
www.eeworm.com/read/16360/670554
vhw c.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:35:19 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
www.eeworm.com/read/16360/670610
vhw cc.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:54:03 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
www.eeworm.com/read/17937/767676
tf bin2gra_tb.tf
module testbench();
// Inputs
reg [7:0] Bin;
// Outputs
wire [7:0] Gry;
// Instantiate the UUT
bin2gra uut (.Gry(Gry), .Bin(Bin));
reg [7:0] i;
// Initialize Inputs
www.eeworm.com/read/17937/767678
tf ram16x8sng_tb.tf
module testbench();
// Inputs
reg clk;
reg we;
reg [3:0] ADDR;
reg [7:0] Din;
// Outputs
wire [7:0] Dout;
// Instantiate the UUT
RAM16x8sng uut (
www.eeworm.com/read/17937/767684
tf counter_simtb.tf
module testbench();
// DATE: Mon Apr 28 15:26:36 2003
// TITLE:
// MODULE: counter_sim
// DESIGN: counter_sim
// FILENAME: counter_sim
// PROJECT: counter_sim
// VERSION: V
www.eeworm.com/read/17937/767691
tf gra2bin_tb.tf
module testbench();
// Inputs
reg [7:0] Gry;
// Outputs
wire [7:0] Bin;
// Instantiate the UUT
gra2bin uut (.Gry(Gry), .Bin(Bin));
reg [7:0] i;
// Initialize Inputs
www.eeworm.com/read/18164/778565
vhd synth_test.vhd
--TESTBENCH FOR THE ENTIRE PROCESSOR. FOR SYNTHESIS THIS FILE WITHOUT
-- THE STIMULUS PART IS GIVEN AS THE TOP LEVEL ENTITY.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.
www.eeworm.com/read/18767/801427
vhd synth_test.vhd
--TESTBENCH FOR THE ENTIRE PROCESSOR. FOR SYNTHESIS THIS FILE WITHOUT
-- THE STIMULUS PART IS GIVEN AS THE TOP LEVEL ENTITY.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.
www.eeworm.com/read/18767/801451
vhd synth_test.vhd
--TESTBENCH FOR THE ENTIRE PROCESSOR. FOR SYNTHESIS THIS FILE WITHOUT
-- THE STIMULUS PART IS GIVEN AS THE TOP LEVEL ENTITY.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.