代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/104415/15694405
txt gencrc.v.txt
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol,
www.eeworm.com/read/158843/10724440
lib~ contents.lib~
58
~E 1 "g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cordic_testbench_struct.vhd" 13 cordic_testbench
~E 1 "g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cord
www.eeworm.com/read/176099/9516750
vhdl input.vhdl
-- $Id: input.vhdl,v 1.1.1.1 2005/01/04 02:06:00 arif_endro Exp $
-- **************************************************************
-- Arif E. Nugroho
-- [20041110]
-- * Derived from testbench from mo
www.eeworm.com/read/424880/10403924
scr run_sim.scr
#!/bin/csh -f
# GLOBAL VARIABLES
###################
set sim_top = testbench;
set arg_tool = "NCSim"; # By default NCSim is used as simulation tool
set arg_wave = 0; # By defa
www.eeworm.com/read/470365/6919427
v test.v
// Testbench for Micron SDR SDRAM Verilog models
`timescale 1ns / 1ps
module test;
reg [31 : 0] dq; // SDRAM I/O
reg [10 : 0] addr;
www.eeworm.com/read/458164/7303057
vhd demod.vhd
-- demod.vhd QAM demodulator design, intended to illustrate Tcl testbench
--
-- rev 1.0, 03 April 2002, Jonathan Bromley
-- first attempt
--
-- rev 1.1, 17 April 2002, Jonathan Bromley
-- a
www.eeworm.com/read/457421/7325653
v test.v
// Testbench for Micron SDR SDRAM Verilog models
`timescale 1ns / 1ps
module test;
reg [31 : 0] dq; // SDRAM I/O
reg [10 : 0] addr;
www.eeworm.com/read/326417/13143246
v test.v
// Testbench for Micron SDR SDRAM Verilog models
`timescale 1ns / 1ps
module test;
reg [31 : 0] dq; // SDRAM I/O
reg [10 : 0] addr;
www.eeworm.com/read/17937/767667
tf cnt99_tb.tf
module testbench();
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] one_out;
wire [3:0] ten_out;
// Instantiate the UUT
counter uut (
.clk(clk),
www.eeworm.com/read/198135/5089711
scr run_sim.scr
#!/bin/csh -f
# GLOBAL VARIABLES
###################
set sim_top = testbench;
set arg_tool = "NCSim"; # By default NCSim is used as simulation tool
set arg_wave = 0; # By defa