代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
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asm testbench_arch.asm
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bak testbench.v.bak
`timescale 1ns/1ns
module testbench;
reg clk;
reg rst;
reg codein;
wire [1:0] codeoutv;
wire [1:0] codeoutb;
initial
begin
clk
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ndo can_testbench.ndo
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model for Module can_top
vcom -87 -explicit can_t
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udo can_testbench.udo
## Project Navigator simulation template: can_testbench.udo
## You may edit this file to control your simulation.
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v can_testbench.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"
module can_testbench();
parameter Tp = 1;
paramet
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fdo can_testbench.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jan 11 10:15:14 中国标准时间 2005
##
vlib work
vlog can_register_asyn_syn.v
vlog can_register_asyn.v
vlog can_regi
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dat testbench_arch.dat
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asm testbench_arch.asm
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vhd working_testbench.vhd
entity TEST_BENCH is
end TEST_BENCH;
use work.all;
architecture AUTOCOR1 of TEST_BENCH is
signal B: BIT_VECTOR(3 downto 0);
signal A: BIT_VECTOR(2 downto 0);
SIGNAL RUN:BIT;
SIGNAL
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vhd testbench_fa.vhd
entity TEST_BENCH is
end TEST_BENCH;
use work.all;
architecture AUTOCOR1 of TEST_BENCH is
signal B: BIT_VECTOR(3 downto 0);
signal A: BIT_VECTOR(2 downto 0);
SIGNAL RUN:BIT;
SIGNAL