代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/397063/2404597
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal -radix unsigned /testbench_rsdecoder/recword
add wave -noupdate -format Logic /testbench_rsdecoder/clock1
add
www.eeworm.com/read/397063/2404600
do wave1.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal /testbench_rsdecoder/recword
add wave -noupdate -format Logic /testbench_rsdecoder/clock1
add wave -noupdate -
www.eeworm.com/read/360248/2964203
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /testbench/test_controller/clk
add wave -noupdate -format Logic /testbench/test_controller/reset
add wave -noupd
www.eeworm.com/read/181332/5277082
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider System_Testbench
add wave -noupdate -format Logic -radix hexadecimal /system_testbench/tst_sys_clk
add wave -noupdate
www.eeworm.com/read/324787/13245245
v alu_test.v
//--------------------------------------------------------------------
//
// Design : testbench of alu
//
// File name : alu_test.v
//
// Purpose :
www.eeworm.com/read/319363/13452897
v alu_test.v
//--------------------------------------------------------------------
//
// Design : testbench of alu
//
// File name : alu_test.v
//
// Purpose :
www.eeworm.com/read/211663/15175891
v fft_tb.v
/********************************************************************
butterfly testbench
********************************************************************/
`timescale 1ns/100ps
`define
www.eeworm.com/read/285085/8870645
vhd md_tb.vhd
-- Manchester decoder test bench
-- Xilinx, Inc
-- Jan 26, 2000
library ieee ;
use ieee.std_logic_1164.all ;
entity testbench is end ;
architecture v1 of testbench is
component md
port (rst :
www.eeworm.com/read/285085/8870670
vhd me_tb.vhd
-- Manchester encoder test bench
-- lester sanders
library ieee ;
use ieee.std_logic_1164.all ;
entity testbench is end ;
architecture v1 of testbench is
component me
port (rst : in std_logic
www.eeworm.com/read/373315/9463658
vhd md_tb.vhd
-- Manchester decoder test bench
-- Xilinx, Inc
-- Jan 26, 2000
library ieee ;
use ieee.std_logic_1164.all ;
entity testbench is end ;
architecture v1 of testbench is
component md
port (rst :