代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/32675/1035418
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/40270/1138687
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/464255/1532035
do ac97_core.do
# Simulation environment for testbench_ac97_core
vsim work.testbench_ac97_core
add wave test_no
############################################################
### AC97_core signals
##########
www.eeworm.com/read/464255/1532075
do ac97_core.do
# Simulation environment for testbench_ac97_core
vsim work.testbench_ac97_core
add wave test_no
############################################################
### AC97_core signals
##########
www.eeworm.com/read/231587/4713977
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/221684/4827182
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/216392/4896694
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/199553/5076071
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/327541/3455093
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/276189/4167237
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;