代码搜索:testbench

找到约 2,392 项符合「testbench」的源代码

代码结果 2,392
www.eeworm.com/read/190958/5170221

vhd testbench.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:50:28 04/27/2005 -- Design Name: loopback -- Module Name: testbe
www.eeworm.com/read/190958/5170280

vhd testbench.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:50:28 04/27/2005 -- Design Name: loopback -- Module Name:
www.eeworm.com/read/343627/3218041

udo testbench.udo

## Project Navigator Verilog simulation template: testbench.udo ## You may edit this file to control your simulation.
www.eeworm.com/read/343627/3218058

tf testbench.tf

`timescale 1ns/10ps module testbench(); reg reset; reg clk; wire[31:0] counter; initial begin reset=1; clk=0; #5 reset=0; #5 reset=1; #10000000 $stop; end always #50 clk=~clk;
www.eeworm.com/read/343627/3218601

jhd testbench.jhd

MODULE testbench SUBMODULE prescale_counter
www.eeworm.com/read/343627/3218608

udo testbench.udo

## Project Navigator Verilog simulation template: testbench.udo ## You may edit this file to control your simulation.
www.eeworm.com/read/343627/3218631

tf testbench.tf

`timescale 1ns/10ps module testbench(); reg reset; reg clk; wire[31:0] counter; initial begin reset=1; clk=0; #5 reset=0; #5 reset=1; #10000000 $stop; end always #50 clk=~clk;
www.eeworm.com/read/343627/3218634

tdo testbench.tdo

## NOTE: Do not edit this file. ## Auto generated by Project Navigator for Verilog Post-PAR Simulation ## vlib work ## Compile Post-PAR Model for Module prescale_counter vlog -93 +libext+.v+.ve+
www.eeworm.com/read/340166/3291468

v testbench.v

///////////////////////////////////////////////////////////////////// //// //// //// Testbench for Color Space converters
www.eeworm.com/read/340166/3291485

v testbench.v

///////////////////////////////////////////////////////////////////// //// //// //// Testbench for Color Space converters