代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/400225/11580394
hist save.hist
sim to 0
sim 6000.00ns
scope "t.m "
vprobe LED8[7:0]
scope "t "
vprobe hresetn
scope "t "
vprobe hclk
vprobe --Testbench_Master_Signals
vprobe ( --Testbench_Master_Signals )
scope "t.ahbmst_
www.eeworm.com/read/292000/8383615
vhd txmit_tb.vhd
-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v
www.eeworm.com/read/387422/8684628
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/286093/8788697
vhd fpqaaa.vhd
-- VHDL Test Bench Created from source file fpq.vhd -- 11:00:35 06/11/2007
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
www.eeworm.com/read/364127/9921621
v combi_ckt_tb.v
// Testbench for "CombinationalCircuit" module
//
// Illustrates efficient way to exhaustively test
// a combinational circuit
module CombinationalCircuit_TB;
reg a,b,d,c;
wire y;
// Ins
www.eeworm.com/read/167222/9975020
v test_mux4.v
module testbench_mux4;
wire [7:0] mux4_out,m0_in,m1_in,m2_in,m3_in;
wire [1:0]sel_in;
test_mux4 t4 (mux4_out,m0_in,m1_in,m2_in,m3_in,sel_in);
mux4 m4 (mux4_out,m0_in,m1_in,m2_in,
www.eeworm.com/read/355008/10304698
txt 参考.txt
参考testbench教程/教程/writing testbench/16页 1987和1993的区别（文件类型的声明）
93版定义文件，没有in/out之分了，也可参看这里的图片
这里的VHDL textio和上面文件的textio（包含了synopsys的std_logic_textio）第二十六页，write和read的用法，要和这里的《textio用法比较一下》
www.eeworm.com/read/272617/10951735
vhd txmit_tb.vhd
-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v
www.eeworm.com/read/202633/7124942
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/457415/7325746
vhd test_data_gen.vhd
-- Copyright (C) 2004-2005 Digish Pandya
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License a