代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/364127/9921619
v demo_tb.v
// Testbench for "Demo" module
module Demo_TB;
reg astim; // stimulus for port "a"
wire bmon; // connection to monitor port "b"
// Instantiate the device-under-test
Demo DUT (
.a(astim
www.eeworm.com/read/160189/10559997
entries
/image.bmp/1.1/Fri Jan 7 15:26:46 2005/-kb/
/jpeg_src.zip/1.2/Mon Mar 14 10:34:09 2005/-kb/
/readme.txt/1.1/Mon Mar 14 10:34:10 2005//
D/cores////
D/docs////
D/images////
D/src////
D/testbench////
www.eeworm.com/read/273124/10925477
dsw netts.dsw
Microsoft Developer Studio Workspace File, Format Version 6.00
# WARNING: DO NOT EDIT OR DELETE THIS WORKSPACE FILE!
###############################################################################
www.eeworm.com/read/449305/7509009
do functional.do
#
# rebuild whole project
#
savealltabs
quiet on
setactivelib -work
acom "$DSN\src\generator.asf"
acom "$DSN\src\testbench.vhd"
asim -advdataflow conf_testbench_arch
# initialize simul
www.eeworm.com/read/320300/13428715
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand_flash_testbench is
end nand_flash_testbench;
www.eeworm.com/read/320300/13428718
do wave.do
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal /nand_flash_testbench/t_cntrl
add wave -noupdate -format Literal /nand_flash_testbench/test_vector
add wave -n
www.eeworm.com/read/320300/13428720
transcript
# Reading C:/altera/72_cc/modelsim_ae/tcl/vsim/pref.tcl
# OpenFile "D:/Altera/MAXIIZ update/Design example/AN500/modelsim/nand_interface.mpf"
# Loading project nand_interface
vsim -gui work.nand
www.eeworm.com/read/400225/11580384
cfv demo_amba_for_tb.cfv
// Simucad Generated Commands Start Here
// Simucad define
+define+sse
// Project Settings
+typdelays
-"!file .sav=\"demo_amba_for_tb\""
-"!control .sav=3"
-"!control .enablecache"
-l demo
www.eeworm.com/read/415267/11078872
vht cpld_mpu1.vht
-- VHDL Test Bench Created from source file CPLD_MPU1.vhd -- 02/17/09 15:28:25
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logi
www.eeworm.com/read/430376/8753062
hist save.hist
sim to 0
sim 6000.00ns
scope "t.m "
vprobe LED8[7:0]
scope "t "
vprobe hresetn
scope "t "
vprobe hclk
vprobe --Testbench_Master_Signals
vprobe ( --Testbench_Master_Signals )
scope "t.ahbmst_