代码搜索：testbed

找到约 482 项符合「testbed」的源代码

代码结果 482
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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readme

This is an MICO CSIv2 interoperability test which runs against Adiron CSIv2 Interoperability Testbed. For more information about this Adiron project, please look at http://www.adiron.com/InterOpTes
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www.eeworm.com/read/291752/8397901

txt danpdgm_full.txt

040303_213214 Daniell Periodogram Testbed =========================== Max_Pass_Number = 2000 ar_sig_source Noise_Seed = 113559 Driving_Variance = 0.3 Ar_Order = 2 A_Coeffs[0]
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www.eeworm.com/read/291752/8397910

txt danpdgm_short.txt

040303_213214 Daniell Periodogram Testbed =========================== Max_Pass_Number = 2000 ar_sig_source Noise_Seed = 113559 Driving_Variance = 0.3 Ar_Order = 2 A_Coeffs[0]
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www.eeworm.com/read/291752/8397971

txt bartpdgm_short.txt

040303_210202 Bartlett Periodogram Testbed ============================ Max_Pass_Number = 4000 ar_sig_source Noise_Seed = 113559 Driving_Variance = 0.3 Ar_Order = 2 A_Coeffs[0
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www.eeworm.com/read/291752/8397976

txt bartpdgm_full.txt

040303_210202 Bartlett Periodogram Testbed ============================ Max_Pass_Number = 4000 ar_sig_source Noise_Seed = 113559 Driving_Variance = 0.3 Ar_Order = 2 A_Coeffs[0
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www.eeworm.com/read/291752/8398269

cpp rayleighnoisetest_sim.cpp

// // File = rayleighnoisetest_sim.cpp // #define SIM_NAME "RayleighNoiseTest\0" #define SIM_TITLE "Rayleigh Noise Testbed\0" #include "global_stuff.h" #include "rayleigh_theory.h" #inc
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www.eeworm.com/read/291752/8398286

cpp bartpdgmwind_sim.cpp

// // File = bartpdgm_sim.cpp // #define SIM_NAME "BartPdgmWind\0" #define SIM_TITLE "Windowed Bartlett Periodogram Testbed\0" #include "global_stuff.h" #include "siganchr.h" #include "
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www.eeworm.com/read/290325/8489881

manifesto

TESTBED MANIFESTO Thatcher Ulrich http://tulrich.com I have put this project in the public domain. I considered using one of the standard licenses such as GPL, LGPL or Berkeley/X, b
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www.eeworm.com/read/379944/9171797

v testbench_avlmemory.v

// Testbed for SDRAM model with AVL implementation // written by Chris Fester 4-5-00 `include "AVLMemory.v" `include "Memoryside.v" module top; reg [31:0] outsideAddr; wire [31:0] A; wire [
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www.eeworm.com/read/165580/10057017

cpp rayleighnoisetest_sim.cpp

// // File = rayleighnoisetest_sim.cpp // #define SIM_NAME "RayleighNoiseTest\0" #define SIM_TITLE "Rayleigh Noise Testbed\0" #include "global_stuff.h" #include "rayleigh_theory.h" #inc
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