代码搜索：system verilog
找到约 10,000 项符合「system verilog」的源代码
代码结果 10,000
www.eeworm.com/read/18028/771124
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:34:32 07/21/2007
// Design Name:
/
www.eeworm.com/read/18028/771125
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:03:03 07/20/2007
// Design Name:
/
www.eeworm.com/read/18028/771126
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:54:18 09/23/2007
// Design Name:
/
www.eeworm.com/read/18028/771127
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c8
SET speedgrade = -12
SET simulationfiles = Structural
SET asysymb
www.eeworm.com/read/18028/771128
verilog
www.eeworm.com/read/18028/771129
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:55:16 10/06/2007
// Design Name:
/
www.eeworm.com/read/18028/771130
verilog
radix=10;
coefdata= -55, -27, 9, 45, 73, 87, 84, 61, 25,-18,-58,-87,-96,-83 ,-50, -4,
45, 85, 106, 99, 65, 9,-57, -117, -156, -159, -120, -42, 63, 173, 265, 311,
295, 206, 53, -142, -346, -515, -
www.eeworm.com/read/18028/771131
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:36:33 09/17/2007
// Design Name:
/
www.eeworm.com/read/18028/771132
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:38:08 09/12/2007
// Design Name:
/
www.eeworm.com/read/18028/771133
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c6
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb