代码搜索：system verilog
找到约 10,000 项符合「system verilog」的源代码
代码结果 10,000
www.eeworm.com/read/18028/771114
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c8
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771115
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:45:08 10/05/2007
// Design Name:
/
www.eeworm.com/read/18028/771116
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:13:36 10/05/2007
// Design Name:
/
www.eeworm.com/read/18028/771117
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:13:24 10/05/2007
// Design Name:
/
www.eeworm.com/read/18028/771118
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:13:53 10/05/2007
// Design Name:
/
www.eeworm.com/read/18028/771119
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c8
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771120
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c8
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/18028/771121
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:51:06 09/18/2007
// Design Name:
/
www.eeworm.com/read/18028/771122
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:54:56 07/21/2007
// Design Name:
/
www.eeworm.com/read/18028/771123
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:34:32 07/22/2007
// Design Name:
/