代码搜索：system verilog
找到约 10,000 项符合「system verilog」的源代码
代码结果 10,000
www.eeworm.com/read/18028/771214
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:41:40 08/12/2007
// Design Name:
/
www.eeworm.com/read/18028/771215
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:01:28 07/27/2007
// Design Name:
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www.eeworm.com/read/18028/771216
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:48:29 09/18/2007
// Design Name:
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www.eeworm.com/read/18028/771217
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:24:48 09/17/2007
// Design Name:
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www.eeworm.com/read/18028/771218
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:16:06 09/23/2007
// Design Name:
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www.eeworm.com/read/18028/771219
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:18:35 09/23/2007
// Design Name:
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www.eeworm.com/read/18028/771220
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:32:47 10/09/2007
// Design Name:
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www.eeworm.com/read/18028/771221
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:26:31 09/18/2007
// Design Name:
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www.eeworm.com/read/18028/771222
verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:23:13 10/09/2007
// Design Name:
/
www.eeworm.com/read/18028/771223
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c7
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb