代码搜索：sync
找到约 6,244 项符合「sync」的源代码
代码结果 6,244
www.eeworm.com/read/18360/785693
v can_register_syn.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_syn
( data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default
www.eeworm.com/read/18360/785706
v vga_vtim.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);
// inputs & outputs
input clk; // mast
www.eeworm.com/read/18422/787424
v can_register_syn.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_syn
( data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default
www.eeworm.com/read/18422/787437
v vga_vtim.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);
// inputs & outputs
input clk; // mast
www.eeworm.com/read/18515/792157
v can_register_syn.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_syn
( data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default
www.eeworm.com/read/18515/792170
v vga_vtim.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);
// inputs & outputs
input clk; // mast
www.eeworm.com/read/18518/792790
v can_register_syn.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_syn
( data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default
www.eeworm.com/read/18518/792803
v vga_vtim.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);
// inputs & outputs
input clk; // mast
www.eeworm.com/read/18532/793299
v can_register_syn.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_syn
( data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default
www.eeworm.com/read/18590/796297
v can_register_syn.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_syn
( data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default