代码搜索：sync
找到约 6,244 项符合「sync」的源代码
代码结果 6,244
www.eeworm.com/read/318604/13475140
texi multiboot.texi
\input texinfo @c -*-texinfo-*-
@c -*-texinfo-*-
@c %**start of header
@setfilename multiboot.info
@settitle Multiboot Specification
@c %**end of header
@c Unify all our little indices for now.
@sync
www.eeworm.com/read/303425/13816433
h buffer.h
#ifndef __BUFFER_H_
#define __BUFFER_H_
/* a raydata piece is a pair source, dest */
/* OBSOLETE */
/* keep sync with IASPPHLENGTH (iasp.h) */
/*#define RAYCODE_MAX_STRING_LENGTH 8 */
/* we can mana
www.eeworm.com/read/301022/13870545
c sys_file_table.c
///////////////////////////////////////////////////////////////////////////////
int sys0_sync(void);
int sys0_reload(void);
int sys0_chdriver(void);
int sys0_mkdir(void);
int sys0_rmdir(void)
www.eeworm.com/read/132069/5920843
upp umakefil.upp
### UMAKE PRE-PROCESSOR OUTPUT: DO NOT CHECK INTO CVS
### -*- Mode: Python -*-
### files: symbian.pcf -> Umakefil
UmakefileVersion(2,1)
project.AddDefines("SYNC_RESIZE_OK")
UmakefileVersion(2,1
www.eeworm.com/read/219324/14888005
c bmc_generic52in1.c
#include "..\..\DLL\d_UNIF.h"
#include "..\..\Hardware\h_74xx.h"
static void Sync (void)
{
union
{
struct
{
unsigned CHRbank : 6;
unsigned PRG16 : 1;
unsigned PRGbank : 5;
www.eeworm.com/read/219324/14888009
c bmc_generic20in1a.c
#include "..\..\DLL\d_UNIF.h"
#include "..\..\Hardware\h_74xx.h"
static void Sync (void)
{
union
{
struct
{
unsigned PRG : 4;
unsigned PRGsize : 1;
unsigned PRG16 : 1;
www.eeworm.com/read/8785/153196
v can_register_syn.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_syn
( data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default
www.eeworm.com/read/8785/153209
v vga_vtim.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);
// inputs & outputs
input clk; // mast
www.eeworm.com/read/17812/761272
v can_register_syn.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_syn
( data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default
www.eeworm.com/read/17812/761285
v vga_vtim.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);
// inputs & outputs
input clk; // mast