代码搜索：sync

找到约 6,244 项符合「sync」的源代码

代码结果 6,244
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/248928/4463105

changelog

Build -- Hold lock when creating new H.323 channel to sync the audio channels -- Decrement usage counter when appropriate -- Actually unregister everything in unload_module -- Add IP based authent
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www.eeworm.com/read/239567/4598278

java runinuithread.java

package org.python.pydev.core.uiutils; import org.eclipse.swt.widgets.Display; public class RunInUiThread { public static void sync(Runnable r){ if (Display.getCurrent() == null){ Dis
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www.eeworm.com/read/236543/4639180

1 mplayer.1

.\" MPlayer (C) 2000-2006 MPlayer Team .\" Diese Man-Page wurde/wird von Moritz Bunkus, Sebastian Kr鋗er, .\" Tobias Diedrich gepflegt. .\" .\" In sync with r20358 . .\" -------------------------------
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www.eeworm.com/read/233448/4687004

java gthreadmutex.java

/* GThreadMutex.java -- Implements a mutex object for glib's gthread abstraction, for use with GNU Classpath's --portable-native-sync option. This is used in gthread-jni.c Copyright (C) 2
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www.eeworm.com/read/233448/4688877

java syncfailedexception.java

/* SyncFailedException.java -- a file sync failed Copyright (C) 1998, 1999, 2001, 2002, 2005 Free Software Foundation, Inc. This file is part of GNU Classpath. GNU Classpath is free software; yo
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www.eeworm.com/read/232496/4698725

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity sync_r2w is generic( ADDRSIZE : integer := 4 ); port( wrptr2 : out vl_logic_vector; rptr
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www.eeworm.com/read/232496/4698727

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity sync_w2r is generic( ADDRSIZE : integer := 4 ); port( rwptr2 : out vl_logic_vector; wptr
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www.eeworm.com/read/213877/4910559

changelog

Build -- Hold lock when creating new H.323 channel to sync the audio channels -- Decrement usage counter when appropriate -- Actually unregister everything in unload_module -- Add IP based authent
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www.eeworm.com/read/338256/3319058

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity dcfifo_sync is generic( lpm_width : integer := 1; lpm_widthu : integer := 1; lpm_numwords : integer := 2;
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www.eeworm.com/read/338256/3319084

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity stratixii_lvds_rx_fifo_sync_ram is port( clk : in vl_logic; datain : in vl_logic; write_reset
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