代码搜索:strobe

找到约 441 项符合「strobe」的源代码

代码结果 441
www.eeworm.com/read/373368/9461374

dsn strobe_r16a.dsn

www.eeworm.com/read/11139/201748

nc cc2420strobe.nc

/* * "Copyright (c) 2005 Stanford University. All rights reserved. * * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose, without fee, and w
www.eeworm.com/read/310709/3692135

nc cc2420strobe.nc

/* tab:4 * "Copyright (c) 2005 Stanford University. All rights reserved. * * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose, without
www.eeworm.com/read/289075/3996111

nc cc2420strobe.nc

/* tab:4 * "Copyright (c) 2005 Stanford University. All rights reserved. * * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose, without
www.eeworm.com/read/383940/2607675

nc cc2420strobe.nc

/* * "Copyright (c) 2005 Stanford University. All rights reserved. * * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose, without fee, and witho
www.eeworm.com/read/172784/9690437

c my_strobe_tf.c

/********************************************************************** * $my_strobe example -- C source code using TF PLI routines * * C source to synchronize to the end of a simulation time st
www.eeworm.com/read/172784/9690445

v my_strobe_test.v

/********************************************************************** * $my_strobe example -- Verilog test bench source code * * Verilog test bench to test the $my_strobe PLI application. *
www.eeworm.com/read/172784/9690455

log my_strobe_test.log

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: my_strobe_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Dec 26, 1998 02:01:43 Verilog_XL_Turbo_NT 2.6.9 Dec 26,
www.eeworm.com/read/172784/9690655

c my_strobe_vpi.c

/********************************************************************** * $my_strobe example -- PLI application using VPI routines * * C source to print the simulation time and new value of a sy
www.eeworm.com/read/172784/9690659

v my_strobe_test.v

/********************************************************************** * $my_strobe example -- Verilog HDL test bench. * * Verilog test bench to test the $my_strobe PLI application. * * For