代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/325597/13195024
vhd negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
www.eeworm.com/read/325597/13195061
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/325597/13195071
vhd bcd.vhd
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/325597/13195082
vhd multiplier.vhd
--multiplier.vhd n-bit multiplier
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity multiplier is
generic ( n : integer := 7; nn :
www.eeworm.com/read/325597/13195111
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/325595/13195142
txt 顶层文件.txt
library ieee;
use ieee.std_logic_1164.all;
entity final is
port(clk:in std_logic;
change:in std_logic;
seg:out std_logic_vector(6 downto 0);
sel:out std_logic_vector(3 downto 0);
www.eeworm.com/read/325527/13198610
vhd encdec_8b10b_tb.vhd
-------------------------------------------------------------------------------
--
-- Title : Test Bench for enc_8b10b and dec_8b10b
-- Design : 8b-10b Encoder/Decoder Test Bench
-- Project : 8000
www.eeworm.com/read/325527/13198616
vhd enc_8b10b_tb.vhd
-------------------------------------------------------------------------------
--
-- Title : Test Bench for enc_8b10b
-- Design : 8b/10b Encoder Test Bench
-- Project : 8000 - 8b10b_encdec
-- Au
www.eeworm.com/read/325504/13199793
vhd bcd.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.STD_logic_unsigned.all;
ENTITY bcd IS
PORT(clk:in STD_LOGIC;
a,b:in STD_LOGIC_VECTOR(3 downto 0);
sum:OUT STD_LOGIC_VECTOR(4 downt
www.eeworm.com/read/325484/13201412
vhd vote7.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY vote7 is
PORT (men:IN std_logic_vector(6 downto 0);
stop:buffer std_logic);
END vote7;
ARCHITECTURE behave OF