代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/349548/10819151
vhd seealarm.vhd
-- seealarm, conctrol displaying the alarm modle
Library IEEE;
use IEEE.std_logic_1164.all;
entity seealarm is
port(en:in std_logic;
norm:in std_logic_vector(1 downto 0);
q:out s
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vhd counter4.vhd
--counter4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter4 is
port(clk,clr:in std_logic;
bcd:out std_logic_vecto
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vhd counter3.vhd
--counter3
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter3 is
port(clk,clr:in std_logic;
bcd:out std_logic_vect
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vhd flash.vhd
--flash
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity flash is
port(clk,en:in std_logic;
beam:in std_logic_vector(6 downt
www.eeworm.com/read/349548/10819242
vhd seealarm.vhd
-- seealarm, conctrol displaying the alarm modle
Library IEEE;
use IEEE.std_logic_1164.all;
entity seealarm is
port(en:in std_logic;
norm:in std_logic_vector(1 downto 0);
q:out s
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vhd reg4_1.vhd
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg4_1 is
PORT(d:in std_logic_vector(3 downto 0);
clk : IN std_logic;
q:out std_logic_vector(3 downto 0));
END reg4_1;
ARCHITEC
www.eeworm.com/read/349548/10819426
vhd key_scan.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity key_scan is
port(clk,key_pre:in std_logic;
row:in std_logic_vector(3 downto 0);
www.eeworm.com/read/349548/10819451
vhd test3.vhd
package width is
constant N1:integer:=2;
constant N2:integer:=16;
end width;
USE work.width.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_u
www.eeworm.com/read/349548/10819458
vhd d_flipflop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
datain :in std_logic_vector(7 downto 0);
www.eeworm.com/read/349548/10819485
vhd decoder_3_8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity decoder_3_8 is
port(a,b,c,g1,g2a,g2b:in std_logic;
y:out std_logic_vector(7 downto 0));
end decoder_3_8;
architecture rtl of decoder_3_8