代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/420425/10796111
vhd wishbone_i2c_master.vhd
--
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (tha
www.eeworm.com/read/420360/10800063
vhd test.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:32:58 01/20/2006
-- Design Name: vga
-- Module Name: test
www.eeworm.com/read/275690/10800873
vhd i60bcd.vhd
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity i60bcd i
www.eeworm.com/read/275690/10800961
vhd regne.vhd
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;
entity regne is
generic ( n : integer := 12 ) ;
port (
r : in std_logic_vector(n-1 downto 0) ;--register
www.eeworm.com/read/275690/10801172
vhd negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
www.eeworm.com/read/275690/10801258
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/275690/10801290
vhd bcd.vhd
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/275690/10801305
vhd multiplier.vhd
--multiplier.vhd n-bit multiplier
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity multiplier is
generic ( n : integer := 7; nn :
www.eeworm.com/read/275690/10801409
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/420119/10816015
vhd sumador2.vhd
library ieee;
use ieee.std_logic_1164.all;
ENTITY sumador IS
GENERIC(SIZE: INTEGER);
PORT(a :IN STD_LOGIC_VECTOR(SIZE - 1 downto 0);
b :IN STD_LOGIC_VECTOR(SIZE - 1 downto 0);
cin