代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/357728/10202503
vhd control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/357255/10213122
vhd sel.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sel IS
PORT(clk: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
end sel;
ARCHITECTURE are OF sel
www.eeworm.com/read/357005/10217678
vhd clk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk is
port(
clk : in std_logic;
address : out std_logic_vector(5 downto 0));
end clk;
a
www.eeworm.com/read/357005/10217680
vhd mux2_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux2_1 is
generic(n:integer:=24);
port(
sel:in bit;
A,B:in std_logic;
Y:out std_logic);
end mux2_1;
a
www.eeworm.com/read/357005/10217691
vhd testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
www.eeworm.com/read/357005/10217704
vhd top.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS --顶层设计
PORT ( CLK12MHZ : IN STD_LOGIC;
INDEX1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
www.eeworm.com/read/357005/10217716
vhd csout.vhd
library ieee;
Use ieee.std_logic_1164.all;
Entity csout is
port(data:in std_logic_vector(7 downto 0);
cs:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
end csout;
www.eeworm.com/read/357005/10217719
vhd rxt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity rxt is
port(
mclk_16:in std_logic;--16倍baud
rx:in std_logic;--读，复位，和接收端
data:out std_logic_vector(7 downto
www.eeworm.com/read/356978/10218209
vhd sdr_sdram.vhd
--#######################################################################
--
-- LOGIC CORE: SDR SDRAM Controller
-- MODULE NAME: sdr_sdram()
-- COMPANY: Alte
www.eeworm.com/read/356348/10230754
vhd div248.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div248 is
port(clk:in std_logic;------时钟
div2:out std_logic;-----输出2分频信号
div4:out std_logic;-----输出4分