代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/374530/9399962
vhd reg4_1.vhd
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg4_1 is
PORT(d:in std_logic_vector(3 downto 0);
clk : IN std_logic;
q:out std_logic_vector(3 downto 0));
END reg4_1;
ARCHITEC
www.eeworm.com/read/374530/9399976
vhd reg32bit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg32bit is
port(load:in std_logic;
din:in std_logic_vector(31 downto 0);
dout:out std_logic_vector(31 downto 0));
end reg32bit;
archit
www.eeworm.com/read/374530/9399978
vhd mul16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul16 is
port (clk:in std_logic;
a,b:in std_logic_vector(15 downto 0);
q:ou
www.eeworm.com/read/374530/9400006
vhd key_scan.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity key_scan is
port(clk,key_pre:in std_logic;
row:in std_logic_vector(3 downto 0);
www.eeworm.com/read/374530/9400012
vhd test3.vhd
package width is
constant N1:integer:=2;
constant N2:integer:=16;
end width;
USE work.width.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_u
www.eeworm.com/read/374530/9400016
vhd d_flipflop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
datain :in std_logic_vector(7 downto 0);
www.eeworm.com/read/374530/9400035
vhd decoder_3_8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity decoder_3_8 is
port(a,b,c,g1,g2a,g2b:in std_logic;
y:out std_logic_vector(7 downto 0));
end decoder_3_8;
architecture rtl of decoder_3_8
www.eeworm.com/read/374530/9400049
vhd jioujiaoyan.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jioujiaoyan is
port(a:in std_logic_vector(7 downto 0);
q:out std_logic);
end
www.eeworm.com/read/374530/9400065
vhd dff.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff is
port(a :in std_logic;
b :in std_logic;
sel:in std_logic;
c:out
www.eeworm.com/read/374530/9400143
vhd addr.vhd
--addr (模块)正弦
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr is
port(
clk:in std_logic;
dout:out std_logic_vector(5 downto 0)
);
end ad