代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/376301/9321653
vhd miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
www.eeworm.com/read/376301/9321654
vhd miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
www.eeworm.com/read/179993/9325343
vhd control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/376164/9328693
vhd tennis.vhd
library ieee;
use ieee.std_logic_1164.all;
entity TENNIS is
port(bain,bbin,clr,clk,souclk:in std_logic;
ballout:out std_logic_vector(7 downto 0);
countah,countal,countbh,countbl:out std_logic_v
www.eeworm.com/read/179871/9332981
vhd memory.vhd
--
-- Simple RAM and ROM models
--
-- Written by Jiri Gaisler, ESA/ESTEC, 1996
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use std.textio.all;
entity FLASHP
www.eeworm.com/read/375322/9364081
vhd apex20ke_mf.vhd
--
-- Copyright (C) 1988-1999 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any ot
www.eeworm.com/read/375219/9368300
vhdl 控制器协议层.vhdl
--控制器协议层
--file :usbf_pd.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity usb_pd is --实体声明
generic(
www.eeworm.com/read/374530/9399638
vhd mux2_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux2_1 is
generic(n:integer:=24);
port(
sel:in bit;
A,B:in std_logic;
Y:out std_logic);
end mux2_1;
a
www.eeworm.com/read/374530/9399662
vhd testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
www.eeworm.com/read/374530/9399716
vhd rxt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity rxt is
port(
mclk_16:in std_logic;--16倍baud
rx:in std_logic;--读，复位，和接收端
data:out std_logic_vector(7 downto