代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/281861/9128642
vhd alarmreg.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY alarmreg IS
PORT(alarmload : IN STD_LOGIC; --并行加载的控制信号
clk : IN STD_LOGIC; --全局时钟
buffertime : IN STD_LOGIC_VECTOR(23
www.eeworm.com/read/281861/9128644
vhd counter.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter IS
PORT(clk : IN STD_LOGIC; --全局时钟
load : IN STD_LOG
www.eeworm.com/read/281861/9128684
vhd and2.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and2 IS
PORT(
aa,bb : IN STD_LOGIC;
yy : OUT STD_LOGIC);
END and2;
ARCHITECTURE behavier OF and2 IS
BEGIN
yy
www.eeworm.com/read/281861/9128720
vhd bidir_bus.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bidir_bus IS
PORT(
a,b : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); --数据,宽度8位
en : IN STD_LOGIC;
www.eeworm.com/read/281861/9128723
vhd and8_use_and2_test.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and8_use_and2_test IS
PORT(
a1,a2,a3,a4,a5,a6,a7,a8 : IN STD_LOGIC;
y : OUT STD_LOGIC);
END and8_use_and2_test;
ARCHITECTURE be
www.eeworm.com/read/281861/9128744
vhd or2.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY or2 IS
PORT(
a,b : IN STD_LOGIC;
y : OUT STD_LOGIC);
END or2;
ARCHITECTURE behavier OF or2 IS
BEGIN
y
www.eeworm.com/read/281861/9128747
vhd not_gate.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY not_gate IS
PORT(
a : IN STD_LOGIC;
y : OUT STD_LOGIC);
END not_gate;
ARCHITECTURE behavier OF not_gate IS
BEGIN
y
www.eeworm.com/read/281861/9128825
vhd disp_buf.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY disp_buf IS
PORT(
clk : IN STD_LOGIC; --全局时钟
ld : IN STD_LOGIC; --同步加载使能
data : IN STD
www.eeworm.com/read/183580/9152982
vhd idec.vhd
--
-- Risc5x
-- www.OpenCores.Org - November 2001
--
--
-- This library is free software; you can distribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as pu
www.eeworm.com/read/379498/9194833
vhd traffic.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity traffic is
port(clk : in std_logic;
ql : out std_logic_vector(7 downto 0);