代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/426972/8988327
vhd gh_fir_filter_fg.vhd
---------------------------------------------------------------------
-- Filename: gh_FIR_filter_fg.vhd
--
-- Description:
-- FIR Filter with full generics
--
-- Copyright (c) 2007 by George
www.eeworm.com/read/426972/8988332
vhd gh_tvfd_filter.vhd
---------------------------------------------------------------------
-- Filename: gh_TVFD_filter.vhd
--
-- Description:
-- Time Varying Fractional Delay Filter
--
-- Copyright (c) 2005, 20
www.eeworm.com/read/426972/8988402
vhd gh_pwm.vhd
-----------------------------------------------------------------------------
-- Filename: gh_PWM.vhd
--
-- Description:
--
-- Copyright (c) 2009 by George Huber
-- an OpenCores.org Project
-
www.eeworm.com/read/426972/8988492
vhd gh_wdt.vhd
-----------------------------------------------------------------------------
-- Filename: gh_wdt.vhd
--
-- Description:
-- watch dog timer
--
-- Copyright (c) 2008 by George Huber
-- an Ope
www.eeworm.com/read/426972/8988564
vhd gh_mux_4to1.vhd
-----------------------------------------------------------------------------
-- Filename: gh_MUX_4to1.vhd
--
-- Description:
-- a 4 to 1 mux
--
-- Copyright (c) 2005 by George Huber
-- an
www.eeworm.com/read/426972/8988679
vhd gh_jkff.vhd
-----------------------------------------------------------------------------
-- Filename: gh_jkff.vhd
--
-- Description:
-- a JK Flip-Flop
--
-- Copyright (c) 2005 by George Huber
-- an Ope
www.eeworm.com/read/164129/8996449
vhd decoder_3_8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity decoder_3_8 is
port(a,b,c,g1,g2a,g2b:in std_logic;
y:out std_logic_vector(7 downto 0));
end decoder_3_8;
architecture rtl of decoder_3_8
www.eeworm.com/read/164129/8996469
vhd jioujiaoyan.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jioujiaoyan is
port(a:in std_logic_vector(7 downto 0);
q:out std_logic);
end
www.eeworm.com/read/164129/8996486
vhd dff.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff is
port(a :in std_logic;
b :in std_logic;
sel:in std_logic;
c:out
www.eeworm.com/read/426736/9002522
vhd clk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk is
port(
clk : in std_logic;
address : out std_logic_vector(5 downto 0));
end clk;
a