代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/211745/15174658
vhd lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
www.eeworm.com/read/168399/5447257
vhd bram_fifo.vhd
-------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/18 15:30:22 wirthlin Exp $
-------------------------------------------------------
www.eeworm.com/read/168399/5447266
vhd standalone.vhd
-------------------------------------------------------------------------------
-- Filename: standalone.vhd
--
-- Description: Sample circuit for doing audio standalone
--
-- VHDL-Sta
www.eeworm.com/read/471164/6898603
vhd behavioral.vhd
-- hds header_start
-- ==============================================================================
-- Cordic Tester
--
-- This library is free software; you can redistribute it and/or modify
www.eeworm.com/read/471164/6898615
vhd cordic_tester_behavioral.vhd
-- hds header_start
-- ==============================================================================
-- Cordic Tester
--
-- This library is free software; you can redistribute it and/or modify
www.eeworm.com/read/369325/9654879
vhd lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
www.eeworm.com/read/415944/11046956
vhd clk_half.vhd
--provide a 12000000Mhz frequency's clock
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY clk_half IS
PORT(
clk : IN STD_LOGIC;
www.eeworm.com/read/248277/12585859
vhd butterfly1.vhd
library lpm;
use lpm.lpm_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity butterfly1 is
generic(w2:in
www.eeworm.com/read/248277/12586454
vhd lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
www.eeworm.com/read/179335/9360362
tex classelement__parser_3_01std_1_1string_01_4.tex
\section{element\_\-parser$$ Class Template Reference}
\label{classelement__parser_3_01std_1_1string_01_4}\index{element_parser< std::string >@{element\_\-parser$$}}