代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
www.eeworm.com/read/147571/12545517

vhd display_6_led.vhd

--display_6_led.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity display_6_led is port(din0: in std_logic_vector(3 downto 0); din1: in std_logic_ve
www.eeworm.com/read/335194/12546122

vhd dff89.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff89 IS PORT( clk : IN STD_LOGIC; clear : IN STD_LOGIC; Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Dout : OUT STD_LOGIC_VECTO
www.eeworm.com/read/335194/12546129

vhd dff15.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff15 IS PORT( clk : IN STD_LOGIC; clear : IN STD_LOGIC; Din : IN STD_LOGIC_VECTOR(15 DOWNTO 0); Dout : OUT STD_LOGIC_VECT
www.eeworm.com/read/335194/12546496

vhd dff8.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff8 IS PORT( clk : IN STD_LOGIC; clear : IN STD_LOGIC; Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Dout : OUT STD_LOGIC_V
www.eeworm.com/read/147245/12571970

vhd mc8051_ramx_.vhd

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www.eeworm.com/read/147245/12572003

vhd mc8051_rom_.vhd

------------------------------------------------------------------------------- -- -- -- X X XXXXXX XXXXXX
www.eeworm.com/read/248288/12585438

txt weideng.txt

library ieee; use ieee.std_logic_1164.all; entity kz is port(left,right:in std_logic; lft,rit,lr:out std_logic); end kz; architecture kz_arc of kz is begin process(left,right)
www.eeworm.com/read/248277/12585933

vhd txmittest.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity txmittest is port( tx:out std_logic; txclkout:out std_logic;--For test send clok; data:in std_logic_vecto
www.eeworm.com/read/248277/12586087

vhd xor32.vhd

--xor32 library IEEE; use IEEE.std_logic_1164.all; use Ieee.std_logic_unsigned.all; use Ieee.std_logic_arith.all; entity xor32 is port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
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vhd xor32.vhd

--xor32 library IEEE; use IEEE.std_logic_1164.all; use Ieee.std_logic_unsigned.all; use Ieee.std_logic_arith.all; entity xor32 is port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);