代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/252132/12300581
vhd components.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE components IS
COMPONENT mux2to1 -- 2-to-1 multiplexer
PORT ( w0, w1 : IN STD_LOGIC ;
s : IN STD_LOGIC ;
f : OUT STD_LOGIC );
www.eeworm.com/read/252132/12300598
vhd shiftlne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- right-to-left shift register with parallel load and enable
ENTITY shiftlne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT( R : IN STD_LOGIC_VECTOR
www.eeworm.com/read/252132/12300604
vhd regne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN
www.eeworm.com/read/252132/12300609
vhd sort.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.components.all ;
ENTITY sort IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( Clock, Resetn : IN STD_LOGIC ;
s, WrInit, Rd : IN STD_LOGIC ;
www.eeworm.com/read/252132/12300614
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
-- n-bit register with enable
COMPONENT regne
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1
www.eeworm.com/read/252132/12300616
vhd regne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN
www.eeworm.com/read/252132/12300622
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
-- D flip-flop with 2-to-1 multiplexer connected to D
COMPONENT muxdff
PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ;
www.eeworm.com/read/252132/12300626
vhd shiftlne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- right-to-left shift register with parallel load and enable
ENTITY shiftlne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT( R : IN STD_LOGIC_VECTOR
www.eeworm.com/read/252132/12300628
vhd shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
www.eeworm.com/read/252132/12300639
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
-- 2-to-1 multiplexer
COMPONENT mux2to1
PORT ( w0, w1 : IN STD_LOGIC ;
s : IN STD_LOGIC ;
f : OUT STD_L