代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/198238/7946483
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/398431/7947128
vhd grfpwxsh.vhd
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free
www.eeworm.com/read/398431/7947143
vhd grfpushwx.vhd
-----------------------------------------------------------------------------
-- Entity: grfpushwx
-- File: grfpushwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU (shared ver
www.eeworm.com/read/398431/7947156
vhd mfpwx.vhd
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free
www.eeworm.com/read/398431/7947174
vhd grlfpwx.vhd
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free
www.eeworm.com/read/398431/7947196
vhd grfpwx.vhd
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free
www.eeworm.com/read/298078/7975164
vhd cnt30.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT30 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S3:OUT STD_LOGIC;
LOAD:IN BIT;
Q3
www.eeworm.com/read/298078/7975188
vhd cnt25.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT25 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S2:OUT STD_LOGIC;
LOAD:IN BIT;
Q2
www.eeworm.com/read/298078/7975363
vhd cnt5.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT5 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S1:OUT STD_LOGIC;
LOAD:IN BIT;
Q1:
www.eeworm.com/read/298078/7975428
vhd cnt50.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT50 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S5:OUT STD_LOGIC;
LOAD:IN BIT;
Q5