代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/184671/9086659
vhd juntos.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/381138/9107874
vhd cpu.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:16 01/04/2008
-- Design Name:
-- Module Name: CPU - Beha
www.eeworm.com/read/381044/9113222
vhd txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto
www.eeworm.com/read/381044/9113384
vhd xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
www.eeworm.com/read/381044/9113436
vhd xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
www.eeworm.com/read/381044/9113765
vhd division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
www.eeworm.com/read/184270/9113768
vhd nco.vhd
-----------------------------------------------------------------------------
-- Project Name : NCO
www.eeworm.com/read/381044/9113860
vhd bsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto
www.eeworm.com/read/281861/9128617
vhd addern8.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity addern8 Is
GENERIC(datawidth:Integer:=8);
port(
cin : in std_logic;
a: in std_logic_vector(datawidth-1
www.eeworm.com/read/281861/9128708
vhd mux3_8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux3_8 is PORT(
a, b, c, d,e,f,g,h: IN STD_LOGIC; --输入8路。
s: IN STD_LOGIC_VECTOR(2 DOWNTO 0); --地址信号