代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/461262/7230974
xco shift16.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c11
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/460213/7255304
vhd shift_add.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity shift_add is
port(indata:in std_logic_vector(10 downto 0);
clk:in std_logic;
add_en: in std_logic;
www.eeworm.com/read/460213/7255647
vhd shift8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity shift8 is
port(a,clk1,clr1:in std_logic;
b:out std_logic);
end shift8;
architecture rtl of shift8 is
component dff4
port(clk,clr,d:in std_
www.eeworm.com/read/460207/7255747
bak shift.v.bak
module shift(data_out,data_in,rst_,clk);
output[3:0]data_out;
input data_in;
input rst_;
input clk;
reg[3:0]data_out;
always@(posedge clk or negedge rst_)
if(!rst_)
www.eeworm.com/read/459121/7282324
bsf shift_clk.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/459121/7282380
v shift_clk.v
module shift_clk(clkl,clkh,rst,clk_shift);
input clkl;
input clkh;
input rst;
output clk_shift;
reg clk_shift;
reg ttp;
always @(posedge clkh or negedge rst)
begin
if(!rst)
begin
www.eeworm.com/read/458142/7303781
vhd shift_add.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity shift_add is
port(indata:in std_logic_vector(10 downto 0);
clk:in std_logic;
add_en: in std_logic;
www.eeworm.com/read/453519/7417725
c led_shift.c
#include
/*
************************************************************************************************************
函 数 名：void Shift_Left_One_bit(void)
www.eeworm.com/read/453519/7417750