代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/38039/1089255
jpg weight_shift_stand.jpg
www.eeworm.com/read/40270/1138881
vhd shift_register_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : Test Bench for shift_register
-- Design : UART
-- Author : Xinghua
www.eeworm.com/read/40270/1138896
jhd shift_register_tb.jhd
MODULE shift_register_tb
SUBMODULE shift_register
www.eeworm.com/read/492491/1173378
vhd shift_register1.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity shift_register1 is
-- 类属参数
generic (
TOTAL_BIT : integer := 69 );
-- 端口
port (
clk : in std_logic;
reset_n : in std_l
www.eeworm.com/read/487718/1234956
vhd 43_shift_reg.vhd
--************VHDL********************
-- Module : 4-bit register
-- Name : register.vhd
-- Purpose: architecture of 4bit register
-- Comes from: XueYuan publication
-- Date: 1998,9,29
--****
www.eeworm.com/read/487201/1240905
asm shift32r.asm
;-----------------------------------------------------------------;
; This routine shifts the 32-bit pointed to by R0 right once, ;
; returning the low bit in C.
www.eeworm.com/read/487201/1240915
asm shift32s.asm
;-----------------------------------------------------------------;
; This routine shifts the signed 32-bit value pointed to ;
; by R0, right or left an arbitrary amount.
www.eeworm.com/read/487201/1240917
asm shift32l.asm
;-----------------------------------------------------------------;
; This routine shifts the 32-bit pointed to by R0 left once, ;
; returning the high bit in C.
www.eeworm.com/read/483857/1274583
xco shift_reg2.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\work\ISE\c11
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym