代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/260834/11699532
v b_shift1.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module B_SHIFT1 (b1_out,
b1_in
);
parameter BWIDTH=32;
output [0:BWIDTH-1] b1_o
www.eeworm.com/read/260834/11699548
v bk_shift0.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module BK_SHIFT0 (b0_out,
b0_in
);
parameter BWIDTH=32;
output
www.eeworm.com/read/259452/11789712
vhd shift_register_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : Test Bench for shift_register
-- Design : UART
-- Author : Xinghua
www.eeworm.com/read/155822/11844981
cnf shift_control(1).cnf
www.eeworm.com/read/155822/11845229
cnf shift_control(2).cnf
www.eeworm.com/read/258642/11848843
v universal_shift_reg.v
module Universal_Shift_Reg (Data_Out, MSB_Out, LSB_Out, Data_In,
MSB_In, LSB_In, s1, s0, clk, rst);
output [3: 0] Data_Out;
output MSB_Out, LSB_Out;
input [3: 0] Data_In;
inpu
www.eeworm.com/read/258642/11848878
v shift_reg_pa.v
// Note: This model corrects the model on p. 159
module shiftreg_PA (E, A, clk, rst);
output A;
input E;
input clk, rst;
reg A, B, C, D;
always @ (posedge clk or posedge rst
www.eeworm.com/read/258642/11848945
v shift_reg4.v
module Shift_reg4 (Data_out, Data_in, clock, reset);
output Data_out;
input Data_in, clock, reset;
reg [3: 0] Data_reg;
assign Data_out = Data_reg[0];
always @ (negedge reset
www.eeworm.com/read/258642/11848976
v universal_shift_reg.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|12 Jun 2002 17:16:28 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{3537FEE7-1C94-4F93-8B7D-BD878D33C680}
vti_cacheddtm:TX|12 Jun 2002 17
www.eeworm.com/read/258642/11849032
v shift_reg_pa.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|28 Aug 2002 21:35:50 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{DEA61FEB-3B8D-4D51-8341-611642A01A53}
vti_cacheddtm:TX|28 Aug 2002 21